256k x 16 static ram cy7c1041bnv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06434 rev. ** revised february 1, 2006 1cy7c1041bnv33 features ?high speed ?t aa = 12 ns ? low active power ? 612 mw (max.) ? low cmos standby power (commercial l version) ? 1.8 mw (max.) ? 2.0v data retention (660 w at 2.0v retention) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features functional description the cy7c1041bnv33 is a hi gh-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory loca tion specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the output s are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041bnv33 is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and grou nd (revolutionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k x 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 1024 x 4096 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce we ble bhe top view soj tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [1] .... ?0.5v to +4.6v dc voltage applied to outputs in high z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma selection guide -12 -15 maximum access time (ns) 12 15 maximum operating current (ma) comm?l 190 170 ind?l - 190 maximum cmos standby current (ma) com?l/ind?l 8 8 com?l l0.5 0.5 operating range range ambient temperature [2] v cc commercial 0c to +70c 3.3v 0.3v industrial ?40c to +85c electrical characteristics over the operating range parameter description test conditions -12 -15 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.5 2.2 v cc +0.5 v v il input low voltage [1] ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ma i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ma i cc v cc operating supply current v cc = max., f = f max = 1/t rc comm?l 190 170 ma ind?l - 190 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v,or v in < 0.3v, f = 0 com?l/ind?l 8 8 ma com?l l 0.5 0.5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 8 pf ac test loads and waveforms notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. tested initially and after any design or proc ess changes that may affect these parameters. 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope output (a) (b) r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v rise time: 1 v/ns fall time: 1 v/ns [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 3 of 8 switching characteristics [4] over the operating range -12 -15 parameter description min. max. min. max. unit read cycle t rc read cycle time 12 15 ns t aa address to data valid 12 15 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 12 15 ns t doe oe low to data valid 6 7 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [5, 6] 67ns t lzce ce low to low z [6] 33 ns t hzce ce high to high z [5, 6] 67ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 12 15 ns t dbe byte enable to data valid 6 7 ns t lzbe byte enable to low z 0 0 ns t hzbe byte disable to high z 6 7 ns write cycle [7, 8] t wc write cycle time 12 15 ns t sce ce low to write end 10 12 ns t aw address set-up to write end 10 12 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 10 12 ns t sd data set-up to write end 7 8 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [6] 33 ns t hzwe we low to high z [5, 6] 67ns t bw byte enable to end of write 10 12 ns data retention characteristics over the operating range (for l version only) parameter description conditions [10] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 330 a t cdr [3] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is m easured 500 mv from steady-stat e voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 9. t r < 3 ns for the -12 and -15 speeds. 10. no input may exceed v cc + 0.5v. [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 4 of 8 data retention waveform switching waveforms read cycle no. 1 [11, 12] read cycle no. 2 (oe controlled) [12, 13] notes: 11. device is continuously selected. oe , ce , bhe and/or bhe = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce impedance address data out v cc supply t dbe t lzbe t hzce bhe ,ble current i sb i cc [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 5 of 8 write cycle no. 1 (ce controlled) [14, 15] write cycle no. 2 (ble or bhe controlled) notes: 14. data i/o is high-impedance if oe or bhe and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high?impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o ce we t address bhe , ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o bhe ,ble we ce address [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 6 of 8 write cycle no. 3 (we controlled, oe low) truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 cy7c1041bnv33-12vxc 51-85082 44-l ead (400-mil) molded soj (pb-free) commercial cy7c1041bnv33l-12vxc 51-85082 44-lead (400-mil) molded soj (pb-free) cy7c1041bnv33l-12vc 51-85082 44-lead (400-mil) molded soj cy7c1041bnv33l-12zc 51-85087 44-pin tsop ii z44 cy7c1041bnv33l-12zxc 51-85087 44-pin tsop ii z44 (pb-free) 15 cy7c1041bnv33-15vxc 51-85082 44-lead (400-mil) molded soj (pb-free) commercial CY7C1041BNV33L-15VXC 51-85082 44-lead (400-mil) molded soj (pb-free) cy7c1041bnv33l-15zxc 51-85087 44-pin tsop ii z44 (pb-free) cy7c1041bnv33-15vxi 51-85082 44-lead (400-mil) molded soj (pb-free) industrial please contact local sales representative regarding availability of these parts. switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams 51-85082-*b 44-lead (400-mil) molded soj (51-85082) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1041bnv33 document #: 001-06434 rev. ** page 8 of 8 document history page document title: cy7c1041bnv33 256k x 16 static ram document number: 001-06434 rev. ecn no. issue date orig. of change description of change ** 423877 see ecn nxr new data sheet [+] feedback [+] feedback
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